Michael Hartman Email & Phone Number

Phoenix, Arizona Area

Chandler, Az

* Supported Intel Custom Foundry ASIC design kits (22nm, 14nm, 10nm). Tasks included development, training, debug and general support of customer engineers. Primary focus was development. * Primary architect of kit development methodology for ASIC kit (dev-ops). Source code control and branching methods to support various stages of customer product cycles, kit execution (make), unit level testing and test-case procurement. * Co-lead for sign-off STA on C2000/Avoton 22nm SoC.… Show more * Supported Intel Custom Foundry ASIC design kits (22nm, 14nm, 10nm). Tasks included development, training, debug and general support of customer engineers. Primary focus was development. * Primary architect of kit development methodology for ASIC kit (dev-ops). Source code control and branching methods to support various stages of customer product cycles, kit execution (make), unit level testing and test-case procurement. * Co-lead for sign-off STA on C2000/Avoton 22nm SoC. Developed full chip sign-off low power STA flow. * P&R owner of power controller digital design block, responsible for timing and DRC closure. * Assisted P&R lead with developing low power flow methodology (synthesis, P&R). * Synthesis lead for entire SoC that was personally accountable for all block synthesis runs. Show less

Greater Atlanta Area

* Logged over 10 SOC tape-outs in varying technologies from 130nm down to 40nm. Ran diverse tasks along the way such as RTL synthesis, STA, physical prototyping, physical budgeting, formal EQ. * Partnered in physical “black box prototyping” methodology creation. Abstracted as much of the chip as possible to make physical placement easy & fast. Get to full chip timing in an expedient time period. Approximate delay due to physical distances in partition budgeting. * Created partition… Show more * Logged over 10 SOC tape-outs in varying technologies from 130nm down to 40nm. Ran diverse tasks along the way such as RTL synthesis, STA, physical prototyping, physical budgeting, formal EQ. * Partnered in physical “black box prototyping” methodology creation. Abstracted as much of the chip as possible to make physical placement easy & fast. Get to full chip timing in an expedient time period. Approximate delay due to physical distances in partition budgeting. * Created partition budgeting flow and GUI. Handled large permeation of partitions & modes for “logical” and “physical” budgeting. * Designed/Maintained synthesis flow, with DFT insertion (RTL Compiler). Allows for late arriving IP to be synthesized again quickly with predictable QOR. * Member of Cisco ASIC low power team. Created documentation to guide and educate ASIC teams on low power methods and approaches. * Solely implemented structured data path XYCAM macro in 40nm. Performed formal EQ, placement, routing and sign off STA. Efforts were recognized as outstanding and resulted in department level award. * Designed sign off STA flow. Provided for common & consistent way of running, despite stage of chip design. Helped maintain STA wiki to show results. Created new methods to mine STA reports for real and hidden issues.* Worked with primary DFT engineer to develop ATPG flow using TetraMAX. Resulted in easy to use flow that can be handed off to foundry partner for production ATPG run. * Partnered with primary formal EQ engineer to develop & maintain flow. Enabled others less experienced engineers to run formal EQ without having to know all the details. * Designed prototype PCB/FPGA boards for lab IP testing. Oversaw layout, manufacture, bring up and testing of boards. * Was primary interface between ASIC team and network administrator for network planning and roll out. Assisted primary network administrator with Linux network administration. Maintain and plan LSF compute farm. Show less

RTL design. Gate level simulation to support fault grading. Formal EQ checking.