Mohan K. Email & Phone Number

San Jose, Ca, Us

Mountain View, California, United States

Santa Clara, California, United States

Campbell, California, United States

Campbell, California, United States

San Francisco Bay Area

Campbell, California

San Francisco Bay Area

• Designed, micro-architected and integrated several logical/functional SoC units, determined different power domains based on application in multiple ultra-low power chips• Integrated multiple third party IPs such as ARM’s Cortex-M7, QoS blocks, multiple Synopsys designware blocks, various ARM support system blocks, bus arbiters and memory wrappers• Implemented low power design methodologies such as clock gating, power gating, Dynamic Voltage & Frequency scaling(DVFS) scheme and categorizing multiple power domains used in sleep/deep-sleep modes• Supported various post-silicon validation activities such as board bring up, leakage current/voltage measurements, electrical pad characteristics and validating low power functionalities in SOC

Colorado Springs, Colorado Area

• Micro-architected, designed and supported major RTL blocks at IP and SoC level within the I/O Controller Core over three chip generations• Proposed, implemented and optimized design feature to I/O Controller core and implemented in collaboration with the architect resulting in a 20% performance improvement• Collaborated with Firmware, Systems engineering and Product integration teams to propose new change requests, performance enhancements based on customer feedback and issues• Worked with the backend and FPGA teams to overcome issues related to timing violations, exceeding power budgets, CDC violations, Lint and Structural Errors at IP and SoC levels• Verified I/O Controller Core of Raid-On-Chip (ROC) design using directed/random-seed based simulations, assertions using a coverage driven UVM test bench

Greater Los Angeles Area

• FPGA Implementation of the Intel’s Pentium 4 NETBURST architecture in the Tomasulo processor which is 4 way superscalar comprising of various blocks such as Register Alias Table (RAT), Physical Register File, Free Register List (FRL), Reorder Buffer (ROB) with aggressive register reclamation from Free Register list, Return Address Stack (RAS)• Simulated and synthesized the above processor in VHDL using ModelSim and Xilinx Tool under Prof. Gandhi Puvvada

Bengaluru Area, India

• Prepared Business Intelligence reports using IBM’s Cognos 8.2 Reporting Tool, Created Extract Transform and Load (ETL) jobs using IBM’s Data Stage v7.5 ETL Tool• Part of a team which performed coding, requirement analysis, development of Data Stage jobs (ETL) and maintained processes of software development• Wrote test cases in order to check the integrity of the data in the reports and ETL jobs. Acted as Quality Team Leader in the process of delivering the code to the client

Master Of Science, Electrical Engineering (Vlsi Design)

Bachelor Of Engineering, Electronics & Communications