Niraj Jaiswal Email and Phone Number
Niraj Jaiswal is a Multiplier Using Schematic Design at PinE Training Academy of VLSI & Embedded.
Pine Training Academy Of Vlsi & Embedded
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Multiplier Using Schematic DesignPine Training Academy Of Vlsi & EmbeddedBilaspur, Ct, In -
Hardware System Design Using Schematics Design And Verilog Hdl And Its Implementation On Fpga From PPine Training Academy Of Vlsi & Embedded Aug 2023 - Present -
Multiplier Using Schematic DesignPine Training Academy Of Vlsi & Embedded Aug 2023 - PresentImplement a 4-bit signed multiplier using schematic design with the help of Logic Gates, Half & Full Adder,2’s complement & Buffer circuits. Learning: Basics of Digital electronics, how our combinational logic circuit works. TOOL- Xilinx ISE Design. -
Logic Gate VerificationPine Training Academy Of Vlsi & Embedded Aug 2024 - PresentDevelop a testbench using SystemVerilog to verify logic gates like AND, OR, NAND, and NOR. Learning: In this project, I learned about how testbench works and what is the importance of testbench. Tools: Xilinx ISE Design. -
Signed Calculator Using Schematic DesignPine Training Academy Of Vlsi & Embedded Aug 2023 - PresentImplement a calculator using schematic design, and create a calculator using combinational logic like an adder, subtractor, multiplier, divider, multiplexer, demultiplexer, and decoder. Learning: Basics of Digital electronics, how our combinational logic circuit works. Face Difficulties: face difficulties like sometimes making wrong connections and developing logic. Tools: Xilinx ISE Design. -
Counters On FpgaPine Training Academy Of Vlsi & Embedded Aug 2023 - PresentImplement different Counters (Synchronous, Asynchronous, Mod-5, Mod-8, Decade) using Verilog HDL and implement on the FPGA (NAXYS A7). Learning: Basics of sequential logic in digital electronics and Basic of FPGA (NAXYS A7). Tools: Xilinx VIVADO. -
Vhdl (Very High-Speed Integrated Circuit Hardware Description Language)Pine Training Academy Of Vlsi & Embedded Aug 2024 - PresentVHDL (VHSIC Hardware Description Language) is a hardware description language used to design and simulate digital systems. Here is an overview of VHDL design
Niraj Jaiswal Education Details
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Government Engineering College BilaspurB. Tech -
Government Dkp Higher Secondary School KotaFirst -
Pine Training AcademyHardware System Design Using Schematics Design And Verilog Hdl And Its Implementation On Fpga -
Pine Training Academy Vlsi Design DelhiVery High Speed Integrated Circuit Hardware Description Language
Frequently Asked Questions about Niraj Jaiswal
What company does Niraj Jaiswal work for?
Niraj Jaiswal works for Pine Training Academy Of Vlsi & Embedded
What is Niraj Jaiswal's role at the current company?
Niraj Jaiswal's current role is Multiplier Using Schematic Design.
What schools did Niraj Jaiswal attend?
Niraj Jaiswal attended Government Engineering College Bilaspur, Government Dkp Higher Secondary School Kota, Pine Training Academy, Pine Training Academy Vlsi Design Delhi.
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Niraj Jaiswal
Software Engineer @ Samsung Semiconductor | Air 49 Gate Cse'22 | M.Tech Cse'24 @ IitbHowrah -
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2gmail.com, theguardiansindia.com
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