I work as a Senior Software Engineer at Google, focused on building performant infrastructure, both on-device (Android) as well as server (GCP), for federated Machine Learning training. Experience includes ML on-device training infra as well as building infrastructure for Google Meet and GMS-Core.In the past I was a Senior R&D Software Development Engineer at Synopsys, on the ICC II place and route tool.My nine years of tech industry experience includes Java server side, Android and C++ development. I love to work on challenging problems, learn from them and keep growing as an engineer.Technical Skills: Software development, programming, algorithms, Java, C/C++, TCL, Python, PERL, Android, software design.
Nvidia
View- Website:
- nvidia.com
- Employees:
- 41500
- Company phone:
- 916.253.7820
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Senior Software EngineerNvidiaKirkland, Wa, Us
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Senior Software EngineerGoogle Dec 2018 - PresentMountain View, Ca, Us -
Staff Software EngineerSynopsys Inc May 2018 - Dec 2018Sunnyvale, California, Us -
Senior R&D Software EngineerSynopsys Inc Oct 2013 - May 2018Sunnyvale, California, UsEDA Software Development in C++
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Senior Engineer, Asic DesignQualcomm Sep 2011 - Oct 2013San Diego, Ca, UsSnapDragon! -
Advanced Software Design EngineerAltera Mar 2011 - Sep 2011EDA/CAD (Software) Development for Quartus. Was part of team responsible for place and route of large "macro blocks" such as PLLs.- Primarily Software Development in C++- TCL/PERL for regression/testing- Verilog/System-Verilog for board level testing of developed features
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Graduate ResearcherNanocad Lab, Ucla Jan 2010 - Mar 2011Los Angeles, Ca, UsDuring my Masters I was a graduate researcher at the NanoCAD Lab (http://nanocad.ee.ucla.edu/Main/Members) where my research focused on :1. Low Power Arithmetic Design and implementation in Verilog :- RTL-Compiler, NC-SIM, Encounter Place and Route, LEC formal verification- Published at International VLSI Design Conference 2011- P. Kulkarni, P. Gupta, and M. Ercegovac, ``Trading Accuracy for Power with an Underdesigned Multiplier Architecture,'' in Proc. IEEE/ACM International Conference on VLSI Design 20112. Algorithms in C++ for early cell level routing congestion estimation -
Graduate Student (Ee)Nanocad Lab, Ucla Sep 2009 - Mar 2011Los Angeles, Ca, UsI received my Masters degree in Electrical Engineering at UCLA with a focus on digital design and VLSI-CADGPA : 3.75/4.0Coursework :Digital Design – Design of VLSI Circuits and Systems, Advanced Digital Integrated CircuitsVLSI-CAD – Algorithm Design and Analysis, VLSI Design-Manufacturing Interface (DFM), Modeling of VLSI Circuits and Systems, Algorithms for VLSI Design AutomationLogic-Design and Architecture – Arithmetic Logic Design, Advanced Computer Architecture
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Asic Design And Automation Intern - Corporate R&DQualcomm Jun 2010 - Sep 2010San Diego, Ca, UsVHDL Design for Components used in Network-on-Chip interconnectTCL, PERL and MATLAB based flow automationEnhancements to an internal tool for simulated annealing based core placementTraining - Synopsys Design Compiler, MATLAB, VHDL, Verilog
Parag Kulkarni Education Details
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UclaElectrical And Computer Engineering -
Dhirubhai Ambani Instiute Of Information And Communication TechnologyInformation And Communication Technology
Frequently Asked Questions about Parag Kulkarni
What company does Parag Kulkarni work for?
Parag Kulkarni works for Nvidia
What is Parag Kulkarni's role at the current company?
Parag Kulkarni's current role is Senior Software Engineer.
What schools did Parag Kulkarni attend?
Parag Kulkarni attended Ucla, Dhirubhai Ambani Instiute Of Information And Communication Technology.
Who are Parag Kulkarni's colleagues?
Parag Kulkarni's colleagues are İlker Aköz, Alok Mooley, Nic Borensztein, Alberto Milone, Ankita Sudani, Kyle Yan, Andrea (Andi) Mcpadden.
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