Parag Kulkarni Email & Phone Number

Kirkland, Wa, Us

Mountain View, Ca, Us

Sunnyvale, California, Us

Sunnyvale, California, Us

EDA Software Development in C++

San Diego, Ca, Us

SnapDragon!

EDA/CAD (Software) Development for Quartus. Was part of team responsible for place and route of large "macro blocks" such as PLLs.- Primarily Software Development in C++- TCL/PERL for regression/testing- Verilog/System-Verilog for board level testing of developed features

Los Angeles, Ca, Us

During my Masters I was a graduate researcher at the NanoCAD Lab (http://nanocad.ee.ucla.edu/Main/Members) where my research focused on :1. Low Power Arithmetic Design and implementation in Verilog :- RTL-Compiler, NC-SIM, Encounter Place and Route, LEC formal verification- Published at International VLSI Design Conference 2011- P. Kulkarni, P. Gupta, and M. Ercegovac, ``Trading Accuracy for Power with an Underdesigned Multiplier Architecture,'' in Proc. IEEE/ACM International Conference on VLSI Design 20112. Algorithms in C++ for early cell level routing congestion estimation

Los Angeles, Ca, Us

I received my Masters degree in Electrical Engineering at UCLA with a focus on digital design and VLSI-CADGPA : 3.75/4.0Coursework :Digital Design – Design of VLSI Circuits and Systems, Advanced Digital Integrated CircuitsVLSI-CAD – Algorithm Design and Analysis, VLSI Design-Manufacturing Interface (DFM), Modeling of VLSI Circuits and Systems, Algorithms for VLSI Design AutomationLogic-Design and Architecture – Arithmetic Logic Design, Advanced Computer Architecture

San Diego, Ca, Us

VHDL Design for Components used in Network-on-Chip interconnectTCL, PERL and MATLAB based flow automationEnhancements to an internal tool for simulated annealing based core placementTraining - Synopsys Design Compiler, MATLAB, VHDL, Verilog

M.S, Electrical And Computer Engineering

B.Tech, Information And Communication Technology