Patrick James Email & Phone Number

Hillsboro, Oregon

Hillsboro

Jones Farm Campus - Hillsboro, Oregon

Led team to develop and release a DDR Rank Margining tool for Intel Core processor memory interface.Developed a stand alone interface validation tool to test the Direct Media Interface (DMI) and PEG (PCIe Graphics) interfaces

Jones Farm Oregon

* Memory Pathfinding - Led studies in next generation memory technology & hierarchies to include DDR4, NAND caching, embedded DRAM, Phase Change Memory.* Client Platform Definition - Develop memory subsystem characterization methodologies to predict memory power & performance for Mobile client segments. Responsible for segment memory configuration definition (DRAM and NAND)* Memory Technology - Memory Spec development for DDR3 and DDR4 memory technologies. Defined a low power… Show more * Memory Pathfinding - Led studies in next generation memory technology & hierarchies to include DDR4, NAND caching, embedded DRAM, Phase Change Memory.* Client Platform Definition - Develop memory subsystem characterization methodologies to predict memory power & performance for Mobile client segments. Responsible for segment memory configuration definition (DRAM and NAND)* Memory Technology - Memory Spec development for DDR3 and DDR4 memory technologies. Defined a low power refresh mode for DDR4 to reduce memory standby power by as much as 40%. Defind industry power metrics & DRAM power targets to align memory manufacturers to client memory power targets. Show less

Jones Farm (Hillsboro), Oregon

* Design Lead for Thunderbolt SBSD Itanium processor test platform. Develop platform requirements, led team of engineers to develop platform and FPGA. Developed and maintained schedule - meeting organizational goals & timelines* Technical Lead - Intel 2-socket Xeon Server. Led a team of engineers & technicians to develop, test & release to align with Intel Xeon Server CPU schedule. Met all business & technical goals.* Technical Lead - Intel Silicon Reference Platform - Xeon based… Show more * Design Lead for Thunderbolt SBSD Itanium processor test platform. Develop platform requirements, led team of engineers to develop platform and FPGA. Developed and maintained schedule - meeting organizational goals & timelines* Technical Lead - Intel 2-socket Xeon Server. Led a team of engineers & technicians to develop, test & release to align with Intel Xeon Server CPU schedule. Met all business & technical goals.* Technical Lead - Intel Silicon Reference Platform - Xeon based server platform. Conducted and managed routing studies for Memory interface & Intel's Common System Interface (CSI). Managed CPU & Chipset pinmap to align with routing studies. Worked with CPU and Platform architects to define customer reference platform feature set.* Fully Buffered DRAM Riser Board development. Part selection, routing studies, power & performance analysis. Riser Board was part of a Xeon server validation platform.* Xeon Server platform engineer. Responsible for all component select, routing studies, power & performance analysis, test & validation. Worked as a lead, directing responsibilities of engineers and technicians to successfully develop, validate and release platform on schedule. Show less