Sr. Silicon Design Engineer
Current• Lead the design of 1.0V, 1.2V and 1.8V electrostatic discharge(ESD) clamps for state-of-the-art technology node• Performed and documented simulations with ESD accurate models for multiple process nodes• Evaluated and updated charged device model (CDM) spice simulation setup for ESD cells to coincide with TSMC’s recommendation• Performed capacitance extraction for ESD cells, including individual P-cell and N-cell capacitance contribution. Results gave the design team a better approach for the next design• Automated data extraction of simulation results with Python and Perl scripts• Started to create a SQL database with Python to store and sort CDM measurement data accessible to various teams