Prabal S. Email & Phone Number

India

India

Remote

Pre and Post Silicon Validation of Amazon's Next Gen Devices/AI chips

Collaborated with cross-functional teams—Software, Architecture, Design, and Pre-silicon Validation—to strategize meticulous test plans for Mesh IPs. Proficiently authored diverse test cases, including stimulus and corner cases, contributing to tangible progress in the tape-out of Intel processors.Led the development and execution of validation plans using Hybrid FPGA models, Emulators, Virtual Simulation Platforms, and System Validation Platforms, including complex multi-Socket… Show more Collaborated with cross-functional teams—Software, Architecture, Design, and Pre-silicon Validation—to strategize meticulous test plans for Mesh IPs. Proficiently authored diverse test cases, including stimulus and corner cases, contributing to tangible progress in the tape-out of Intel processors.Led the development and execution of validation plans using Hybrid FPGA models, Emulators, Virtual Simulation Platforms, and System Validation Platforms, including complex multi-Socket HW Platforms. Integral to the Pre-Silicon Left Shift initiative, refining Post-si test content and Validation infrastructure.Demonstrated expertise in debugging and root causing domain failures within the Post-Silicon Validation environment. Ensured the delivery of functionally correct design blocks and proactively addressed critical RTL/firmware issues before tape-in, contributing to a robust validation process.Defined diverse Hardware and Software Configurations, ensuring exhaustive feature coverage and crafting Volume Validation recipes for SoC Mesh/Fabric. Contributed significantly to Volume Validation/Regressive testing, employing automated checks and content tuning, resulting in a remarkable 35% reduction in Post-silicon Validation time.Possess expertise in performance measurement utilizing Hardware Performance Monitors, coupled with the ability to streamline and automate the Pre-Silicon validation flow for HPM validation. Achieved an 80% reduction in time, optimizing efficiency and precision in the validation process.Demonstrated a deep understanding of Coherency and Mesh Networks within modern SoC architectures. Leveraged expertise in the Validation of Mesh in Multi-Die processor architecture.Steered Enablement and validation for State of the Art Intel Optane Memory Technology, emphasizing coherency aspects. Demonstrated proficiency in Memory Expansion Techniques using Cxl. cache and Cxl. mem to address memory bottlenecks amid rising compute demand in the server world. Show less

Delved into Post Silicon Validation Environment, exploring Coherency Concepts of multicore complex Server architecture, Network on Chip/Mesh in SoC, HSIO Subsystem, and Memory Subsystem. This deep dive equiped me to contribute meaningfully, showcasing a comprehensive understanding of validation processes, data consistency, interconnectivity design, high-speed I/O interfaces, and memory subsystem intricacies.Poised to apply this knowledge, with a goal to advance these domains in… Show more Delved into Post Silicon Validation Environment, exploring Coherency Concepts of multicore complex Server architecture, Network on Chip/Mesh in SoC, HSIO Subsystem, and Memory Subsystem. This deep dive equiped me to contribute meaningfully, showcasing a comprehensive understanding of validation processes, data consistency, interconnectivity design, high-speed I/O interfaces, and memory subsystem intricacies.Poised to apply this knowledge, with a goal to advance these domains in cutting-edge technological landscapes. Show less

Demonstrated proficiency with the Zebu Emulation Flow, including preparing designs for emulation and understanding key concepts of Zebu Compilation. Applied knowledge effectively by running test cases through Regression using Zebu.

Contributed significantly to the Verification of Intel's cutting-edge Smart NIC Cards, delving into the intersection of innovation and networking technology to enhance performance and intelligence in network interface solutions.Engaged in comprehensive exposure and demonstrated extensive involvement in ASIC Verification Flow, Verification Methodologies, and advanced concepts in constraint random verification. Contributed substantially to diverse aspects of Functional Validation,… Show more Contributed significantly to the Verification of Intel's cutting-edge Smart NIC Cards, delving into the intersection of innovation and networking technology to enhance performance and intelligence in network interface solutions.Engaged in comprehensive exposure and demonstrated extensive involvement in ASIC Verification Flow, Verification Methodologies, and advanced concepts in constraint random verification. Contributed substantially to diverse aspects of Functional Validation, including CDC Abstract View validation, RTL early power Estimation, and Design for Testability (DFT), particularly in areas such as scan insertion and compression and other crucial methodologies.Conducted in-depth analysis and led a targeted approach in analyzing regressive testing areas for improvement, strategically reducing the overall Validation Timespan through techniques such as Selective Regressive Testing.Executed detailed Functional Coverage and Code Coverage analyses for assigned IP, showcasing a commitment to thorough assessment and optimization.Initiated the acceleration of the IP-level CDC Abstract generation process using SpyGlass CDC, enhancing efficiency in CDC Verification at the SoC level.Drove innovation in automating the Errors/Warnings Report generation and Analysis Process, streamlining the identification and waiver of Lint errors and warnings.Played a pivotal role in developing Perl scripts to automate register value mapping between XML and RDL files, and automated validation of Register Read/write processes for designated register sets, contributing significantly to process efficiency and accuracy. Show less

New Delhi Area, India

Actively participated in the development of a Superheterodyne receiver using MATLAB Simulink.