Rajesh Devaraj Email & Phone Number

Bengaluru Area, India

Involved in kernel mode device driver development for GPU, as part of TEGRA-SW team.

Guwahati Area, India

Dual Degrees (M.Tech. + Ph.D.) in Computer Science.M.Tech.: July 2012 to June 2014; Ph.D.: July 2014 to December 2018. Thesis title: "Real-time Scheduler Design for Safety-critical systems: A Supervisory Control Approach" Link: http://gyan.iitg.ernet.in/handle/123456789/1173Guide: Prof. Arnab Sarkar, IIT Kharagpur ( http://www.facweb.iitkgp.ac.in/~arnab/ )Co-Guide: Prof. Santosh Biswas, IIT Bhilai ( https://www.iitbhilai.ac.in/index.php?pid=santosh )Nominated for ACM India Doctoral Dissertation Award (2020) by the Dept. of CSE, IIT Guwahati.Co-authored multiple research articles published at prestigious journals and conferences such as ACM Trans. on Embedded Computing Systems (TECS), IEEE Trans. on Industrial Informatics (TII), IEEE Trans. on Network and Service Management (TNSM), IEEE Trans. on Computers (TC),IEEE Trans. on Parallel and Distributed Systems (TPDS),IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD),IEEE/CAA Journal of Automatica Sinica (JAS), IFAC Automatica, ElsevierJournal of Scheduling (JOSH), SpringerJournal of Systems Architecture (JSA), ElsevierJournal of Supercomputing (JSC), SpringerInternational Journal of Control (IJC), Taylor & FrancisIET Computers & Digital Techniques (CDT),American Control Conference (ACC), European Control Conference (ECC), High Performance Computing and Communications Conference (HPCC), Real-time Distributed Computing Conference (ISORC), VLSI Design.Google scholar page: https://scholar.google.co.in/citations?user=2YgXwZsAAAAJ&hl=enResearchGate profile: https://www.researchgate.net/profile/Rajesh-Devaraj

Chennai Area, India

Worked as FPGA/ASIC Front-end RTL (pre-silicon) Verification Engineer in Aerospace (Flight Control Systems) and Consumer Electronics (Un-manned Vehicle, Multi-Function Printers).Hands-on experience in Test-bench development using VHDL, Verilog and System Verilog. Familiar with EDA tools like Cadence NC-SIM, Modelsim, Synopsys VCS, TransEDA. Involved in the preparation of artifacts for SOI-3 (Stage of Involvement-3) audit for Aerospace related projects.Area of expertise includes Requirements Analysis, Test Plan Preparation, Test-bench Development (system level as well as unit level), Debugging RTL Issues, Coverage Analysis.Worked for Various clients: Flight Control Systems Division of Parker Aerospace, GE Oil & Gas, Hamilton Sundstrand, Xerox Inc.

Dual Degree (M.Tech. + Ph.D.), Computer Science And Engineering, 8.25 / 10 (For M.Tech. Coursework)

B.E., Electronics And Communication, 83%

Degree Awarded by Anna University (AU), Chennai

Hsc, 91.3%

High School, 93.2%