Currently working as Associate Director at SSIR.14 Yrs of expertise in Verification and possess strong knowledge in Verilog and System Verilog and UVM.Responsible for RTL verification of digital IPs and protocol sub-systems. Also, responsibilities include coming up with verification plan, testplans, writing testcases, and debugging.Expertise in System Verilog and HDL based verification methodologies.Have solid hands-on experience in architecting and building HVL based verification environment.Knowledge of Verilog HDL, Functional coverage tools, and perl scripting.