Reda Razouk Email & Phone Number

Santa Clara, California, United States

Santa Clara, California, United States

Managed a worldwide team in Intel’s Global Supply Chain responsible for the external technical operations of Intel’s foundry and OSAT suppliers. Responsibility included new product introduction at leading foundries and OSATs, silicon yield sustaining and yield improvements for all of Intel products where silicon is manufactured externally or packaged externally and ensuring uninterrupted supply due to technical limitations

Santa Clara, California, United States

Managed the integration of the Altera Process Technology Team into the Intel environment within the programmable Solutions Group. Drove the assessment and definition of the SOC technology needs for the next generation FPGAs built on Intel’s 10nm Technology and the process integration of CPUs and FPGAs on a common platform

San Jose, California, United States

Responsible for managing a process technology development teams tasked with working with foundries initially and later on with Intel internal technology development teams on the customization and deployment of process technologies aimed at High performance and low-cost FPGAs. The team in San Jose, Taiwan and Penang Malaysia included Process Technology experts, Device Modeling, Yield optimization and Process targeting and were responsible for maintaining and improving yield on all previous generations of products by continuous improvement of all families of FPGAs

Responsible for managing process technology development teams tasked with the development and deployment of all proprietary processes used by National Semiconductor product lines. Responsibility covers all aspects of process design, characterization, modeling and deployment of the technology at the company’s manufacturing sites in South Portland Maine, Arlington Texas and Glasgow Scotland. Technologies developed include Advanced CMOS and BiCMOS processes for digital logic, Analog Mixed Signal and Power products.

Responsible for the development of Analog proprietary processes used by National Semiconductor product lines. Responsibility covered all aspects of process design, characterization and deployment of the technology at the company’s manufacturing sites in Santa Clara, Salt Lake City and Glasgow Scotland. Technologies developed included Power BiCMOS/DMOS, Bipolar and High speed BiCMOS processes for Analog, Mixed Signal and Power technologies

Manager of a Device Research group, a design support group and later an advanced MOS development group with a team in Sunnyvale and one in Albuquerque New Mexico. Responsibilities included exploratory processes and devices, development of sub-micron technologies for high density memories, and BiCMOS technologies aimed at high speed digital applications including micro-controllers with embedded memory, gate arrays and VLSI logic. Additional responsibilities included device characterization, model parameter extraction, and support for and technology-design trade-offs

Held Several positions at Fairchild including• Manager, BiCMOS Development• Manager, MOS VLSI Research• Sr. Member of Research Staff Device Technology and VLSI Process Integration• Member of Research Staff, Device Technology