• Silicon Reliability lead for next generation process nodes in Foundry Technology.• Skilled in reliability modeling, extrinsic & intrinsic defects, fab process technology, accelerated life testing, and screening techniques.• Best Paper winner in global internal AMD "Technology Showcase" as co-author of "Application of Adaptive High Voltage Stress Testing on 5nm & 7nm Process Nodes".• US Patent "Compensation of Operating Time-Related Degradation of Operating Speed by a Constant Total Die Power Mode" -> http://bit.ly/HellerPatent1• Sole author on 2016 IEEE IRPS conference "Near Neighbor Sort Yield and Wafer Sort Yield Impact on Product Burn-In and a Time-Dependent Reliability Study" -> http://bit.ly/ieeenearneighbor• Skilled in JMP, Weibull++, Excel• Gave keynote invited talk at the 2021 AMD Asia Technology Showcase.

• Semiconductor reliability expert.• Led product reliability efforts on AMD’s 7nm products (datacenter/server, high end desktop, game console,...) including qualification of High Temperature Operating Life-time stress (HTOL) as well as experiments to evaluate the Si-performance degradation impact of Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI).• Led efforts for reducing product burn-in by up to 80% through use of (1) design of experiments, (2) defect density analysis, (3) Near Neighbor statistics, and (4) Weibull statistical modeling.• Developed techniques to skip burn-in based on Near Neighbor and "Known Good Die" techniques.• Helped develop High Voltage Stress (HVS) techniques to enhance product burn-in to balance the tradeoff between yield/cost and outgoing dPPM.

65nm Process Integration and 90nm Front-End-of-Line Device Engineering.

• Design and process of MOCVD compound semiconductor (InAlGaP/GaAs) quantum well and quantum dot lasers and LEDs.• Silicon device physics and Silicon process technology.

College Internship at Sony Semiconductor's SRAM Fab in San Antonio.