Principal Member Of Technical Staff - Reliability Architect
Current• Silicon Reliability lead for next generation process nodes in Foundry Technology.• Skilled in reliability modeling, extrinsic & intrinsic defects, fab process technology, accelerated life testing, and screening techniques.• Best Paper winner in global internal AMD "Technology Showcase" as co-author of "Application of Adaptive High Voltage Stress Testing on 5nm & 7nm Process Nodes".• US Patent "Compensation of Operating Time-Related Degradation of Operating Speed by a Constant Total Die Power Mode" -> http://bit.ly/HellerPatent1• Sole author on 2016 IEEE IRPS conference "Near Neighbor Sort Yield and Wafer Sort Yield Impact on Product Burn-In and a Time-Dependent Reliability Study" -> http://bit.ly/ieeenearneighbor• Skilled in JMP, Weibull++, Excel• Gave keynote invited talk at the 2021 AMD Asia Technology Showcase.