Rich Klein Email & Phone Number

Sunnyvale, Ca

Led Technology Enablement & Design Group, located in Canada, the US, and India. This group has a wide variety of technical responsibilities including:• Advanced Technology development and analysis (10nm and beyond) • Technology Reliability Mechanisms (TDDB, BTI, EM, etc.)• Process Design Kits• Physical Verification and DFM • IP delivery for Standard Cells and Compiled MemoriesWe brought up, debugged, and customized Foundry Process Design Kits, including DFM from GLOBALFOUNDRIES, TSMC, and SEC. These enabled design and production of all of AMD’s products.

Managed technical interface with AMD Fabs and GLOBALFOUNDRIES for every generation of advanced CMOS technology from 130 to 32nm . Responsible for ensuring that Foundry technologies were suitable for AMD microprocessor and APU designs. Worked between the Design Group and the Fab/Foundry to resolve all technical issues relating to Microproscessor products. I also led 6+ internal and external technology investigations including alternate memories (eg, ZRAM) and process debug. Key activities:• ‘Optical’ shrink from 130 to 90nm• OPC introduction and Restricted Design Rules at 65nm• HKMG introduction at 32nm• Extensive on-site debug of 32nm process bringup in Dresden

Focused on technology/design interaction issues for K6-K8 products. As part of actual design team, learned K8 Circuit design flow and designed Reservation Station macro and managed external design teams for PLL and Thermsense macros. Some of the technical issues solved were:• Al to Cu BEOL transition• Introduction and debug of SOI • Design of EXRSTA Macro and managed external macro designs• Successful debug of K8 first siliconExtensive involvement in frequency task force issues, particularly in device/product interactions. Performed technology evaluation of dense memory technologies, including full Cost of Acquisition analysis for an alternate memory technology (TRAM). Drove task force to determine optimum K9 RAM cell. Drove design involvement in reliability analysis for SER, EM/SM, Gate Oxide/HCI.

Sunnyvale, Ca

Managed or directed development of and transfer into manufacturing of several generations of AMD CMOS Logic technologies: CS14 (0.7 m), CS34 (0.35 m), CS44 and derivatives (0.25 m with smaller gate lengths), CS50 (0.18 m Al BEOL). These technologies generated $ Billions of revenue for AMD. Integrated the Fab 25 Austin team into LTD and managed development group across California and Texas. Extensive involvement in inter-company technology alliances: key member of NexGen merger due diligence team; drove successful 486 Foundry effort with DEC at South Queensberry Fab in Scotland. Evaluated TSMC for x86 Foundry (twice); evaluated Motorola technology alliance.

Ph.D., Electrical Engineering

Thesis adviser Prof. Richard Pantell Ranked 29th out of 135 candidates on PhD qualifying exam

M.Sc., Electrical Engineering

B.Sc., Electrical Engineering