Ruchitya Tejaswini Anand Email & Phone Number

Santa Clara, California, Us

Santa Clara, California, Us

• Engineer in AMD's Performance Modeling Team for the Instinct MI accelerators• Focused on the interconnect fabric and memory system• Modeling and analysis of architectural updates and design tradeoffs• Infrastructure to setup and run such studies

Santa Clara, California, Us

• Developed a methodology to effectively profile certain ML applications on GPUs• Assisted in software infrastructure design for performance analysis and data collection• Collaborated with performance architects to analyze simulation data

Austin, Tx, Us

Course: Senior Design Project I.• Students define their Capstone project, create a high-level design and plan to execute a prototype.• Evaluated and helped improve project documentation. Leveraged work experience to guide project definition, literature surveys and technical documentation.

Cupertino, California, Us

• Intern in the memory controller team. Implemented several test-bench components in SV/UVM to capture exhaustive metrics on random stimulus.• Developed an automated flow to ensure various legal system configurations were being exercised across simulations.• Designed tests to verify new subsystem functionality.

Austin, Tx, Us

Course: Software Design and Implementation I.Introduces software design principles and problem solving using code. Teaches structured programming in C/C++, fundamental data structures and asymptotic analysis.Responsibilities:• Design and teach learning modules to expound the concepts taught in lectures• Prepare and conduct quizzes• Maintain and update grading scripts• Proctoring and other miscellaneous course-related activities

San Diego, Ca, Us

• Worked on a long-term project that took a conceptually different approach to monitoring transactions across their lifecycle. Integrated the project into Qualcomm's regression flow and demonstrated a working model. Recognised by the team for this effort.• Brought-up parts of the testbench for a challenging new project. This involved a significant overhaul of existing tests and sequences. Several new features were tested and enabled.

San Diego, Ca, Us

Design Verification Engineer in the DDR Controller Subsystem team.• Owned the verification of several sub-IPs and proprietary protocols across projects. Developed new testbench components, and used functional, toggle and assertion coverage metrics to thoroughly test the subsystem• Worked on a project to reduce the time spent in developing new testbench components. We demonstrated significant time savings in the iterative cycles a DV engineer goes through in bringing-up these components.• Led the DDR subsystem verification effort on a product. Achieved all set targets within tight deadlines.

Houston, Texas, Us

Performed benchmarking of applications handling data extraction, and validated data stored in the back-end. Also worked within a standard testing framework to verify and validate functionality of the UI.

Master Of Science - Ms, Electrical And Computer Engineering

Bachelor’S Degree, Electronics And Communication Engineering