* Designed protocol engine for extremely low power RAIN Gen2 tag SoC with computational capabilityon harvested power.* Lead RTL implementation, power analysis, formal and traditional verification includingCPU/AHB/Gen2-system, clock-domain, reset, PCSM, NVM design/timing/testing and memoryissues.* Mentoring juniors on RTL and verifying IP from first-time contributors.* Design and implementation of system of RFID SoC testing suite that included substantial infrastructuredevelopment in RTL testbench, FPGA system and python based raspberry pi and RAINGen2 reader control for silicon testing, that seamlessly work with one set of test definitions.* Lead engagements with analogue, memory design, back-end implementation teams, managementand external partners to solve various issues including power, design, technology and managementrelated issues.

* Development and verification of a digital variable resampler to support multiple ADC clocks.* Managed various trade-off between low power, performance and design time resulting in (known)bug free silicon and a portable verification script suite to system verification team.* Was an active contributing member to the BLE SIG Direction Finding Working Group and producedinternal detailed design reports to improve silicon modem for future changes.* Undertook an independent study to improve sensitivity and investigated the SNR estimationalgorithms.

* LDPC receiver design: Over 5 years’ experience in LPDC receiver architecture design. Have delivered DOSIS3.1 LDPCs in PRQ silicon. Also designed a generic LDPC receiver covering various standards. Expert in DVB-T2/S2/C2/DMB-T/Ghn/MocA/WiFi LDPC receivers.* DSP block design/implementation: Time/carrier recovery, OFDM channel/noise estimation, WiFi b/n/ac/ax time domain, interpolators/decimators, frontend, backend/MAC interface/FEC functional blocks. Module and system level bit-true modelling in C++/Matlab in Windows/Linux platforms in various communication standards including WiFi b/n/ac/ax, DCOSIS3.1 and DVB-T2* HW implementation: RTL implementation/verification of modules with Verilog/SystemVerilog and synthesis testing for timing and area bounds. * ASIC embedded SW/FW design and implementation: Production SW/FW in C taking into account target, resource, power, timing, volatility and memory constraints. Tensilica targeted C++ programming and profiling including BBE16 vector processor plus data path HW accelerators. FW HAL APIs for ARM11.* ASIC Testing at various levels: 10 years’ experience in complex performance, functional and RTL verification test design with automation and controlled randomisation.Full test suite design; mapping from test parameters to test platform inputs including C++/Matlab model, RTL Registers, FPGA inputs, FW headers, CLI scripts for Silicon and test generator data/control.

* Modelling and simulation of power semiconductor devices (IGBT/MOSFET).* Participation at various levels in European FP6 project ROBUSPIC.* Power electronics system modelling and simulation (Ship and Submarine Electric systems).* Fuel Cell modelling and integration into electrical systems simulations.

Engineering Department teaching assistant.

Various digital designs targeting ASICS and FPGAS mainly using VHDL front end software.