Sam Xia Email & Phone Number

上海市

1. Lead and drive GFX and SOC IPs to optimize power, setting power goals for typical use cases and guiding IP teams to achieve targets.2. Explore and define comprehensive power analysis methodology, driving enhancements in RTL coding quality to improve the PPA bottlenecks.3. Hands-on power reporting flow based on PowerArtist and PTPX, built a visual monitor tool to track and optimize power toward goals, also generated the rich power database per block for thorough analysis.4. Lead a block level power modeling based on ML algorithm, deep dive into the details, like multicolinearity issue, to enhance early stage power estimation accuracy.5. Build early power estimation model for new features, supporting critical decisions on architecture changes and performance projections.

上海市

Engaged in the development of the company's first GPGPU chip, responsible for Level 2 cache subsystem design

上海市

Engaged in a 5G radio unit product development, successfully delivered the receiver subsystem along with a fully automated verification platform.

中国 上海

1. Lead the development of a high frequency trading infrastructure. Dedicated on ultra-low latency system design for parallel trading strategies on Linux(Centos 7), performance optimization at kernel level, TCP/IP stack, JVM.2. Build models for order executions and order-books management, backtesting as well.3. Worked on tick data processing and storage, adopted from exchanges' massive raw data to local uniform-format data, to ensure the efficiency and convenience for modeling.

中国 上海

Lead the delivery of an E-band wireless Fronthaul Outdoor Unit prototype, including architecture design, RF link budget analysis, field testing and performance validation with customer.

中国 上海

1. Lead the FPGA implementation of Digital Front-End system. Successfully delivered many of the company's major shipped commercial 3G/4G products.2. Strong knowledge in radio signal processing, such as DUC, DDC, CFR, DPD, AAGC, DAGC, TPC, ET, etc.3. Expertise in FPGA-based system architecture design, always achieved the best PPA design in the industry, contributing to the exceptional competitiveness of products by providing much lower cost solutions. 4. Hands-on experience in FPGA design across multiple Altera and Xilinx families, from 90nm to 14/16nm, Stratix II, Cyclone III, Arria V, Spantan-6, Kintex-7, Artex-7, Virtex-7, UltraScale+, etc. 5. Engaged in the cutting edge technology research and validation work, in charge of hardware solution or calibration for TX/RX channel reciprocity, Analysis and simulation of phase and amplitude errors on antenna array, final performance verification on FPGA board. 6. FPGA team leader. Member of the company's FPGA design expert team.

中国 广东 深圳

Participated in the development of a prototype of WiMax baseband station, as an algorithm engineer. Was responsible for Uplink design, including timing and frequency synchronization in OFDM System. Wrote MATLAB code for system simulation and performance validation.

学士, 计算机科学与技术

硕士学位, 通信与信息系统