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Shailesh Dave Email & Phone Number
Sr Director ASIC Verification
at
Astera Labs
1 work email found
@asteralabs.com
1 phone found area 669
LinkedIn matched
4 data sources
Profile completeness 100%
Current company
Role
Sr Director ASIC Verification
Location
Fremont, California, United States
Company size
Who is Shailesh Dave? Overview
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Quick answer
Shailesh Dave is listed as Sr Director ASIC Verification at Astera Labs, a company with 602 employees, based in Fremont, California, United States. AeroLeads shows a work email signal at asteralabs.com, phone signal with area code 669, and a matched LinkedIn profile for Shailesh Dave.
Shailesh Dave previously worked as Director Design Verification at Astera Labs and Senior Verification Engineer at Astera Labs. Shailesh Dave holds C.A.P.M, Project Management from Boston University Corporate Education Center.
Company email context
Email format at Astera Labs
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{first}.{last}@asteralabs.com
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AeroLeads found 1 current-domain work email signal for Shailesh Dave. Compare company email patterns before reaching out.
Profile bio
About Shailesh Dave
20+ Years of Design Verification experience, starting with design and verification of small modules to current state of leading a team for verification of a System consisting of multiple FPGAs and ASIC.Worked in SystemVerilog (& UVM ) , C++, Specman ('e), Vera, and bunch of other tools with varying domains.I like architecting Verification environments that are very flexible and maintainable.
Listed skills include Verilog, Asic, Functional Verification, Systemverilog, and 20 others.
Current workplace
Shailesh Dave's current company
Company context helps verify the profile and gives searchers a useful next step.
Astera Labs
15 roles · 28 years
Shailesh Dave work experience
A career timeline built from the work history available for this profile.
Director Design Verification
Current
Aug 2022 - Present
Senior Verification Engineer
Aug 2021 - Aug 2022
Principal Verification Engineer
Apr 2019 - Aug 2021
Sr Verification Manager
Apr 2017 - Apr 2019
Verification Manager
Feb 2014 - Apr 2017
Sr. Verification Lead
Aug 2012 - Mar 2014
Lead Dv Engineer
Leading a 9 member team on Netrowork processor verification using SystemVerilog and UVM.
Jun 2011 - Aug 2012
Lead Consultant - Onsite Champion
Proposed and moved client to constrained-random environment. Spearheaded and Created, along with collegues, from scratch, base library that can was used by all the future projects in the company. At introduction of UVM, again spearheaded and created, along with collegues, methodology and base library for the company.Successfully lead and completed multiple.
May 2006 - Jun 2011
Project Manager
Managed and motivated team to successfully complete client projects. Job done includes, creating schedule, managing human resources, tool resources and schedule for a efficient team work and on-time quality delivery of the product.
2005 - 2006
~1 yr
Project Lead
Einfochips
Lead and delivered on several verification projects including Fibre Channel and PCI Express using state of the art verificiation methodology eRM.
2002 - 2004
~2 yrs
Design & Verification Engineer
Einfochips
Designed and Verification various blocks with initial verification in perl and verilog and slowly moving onto automated testbenches.
Jun 2000 - Jun 2002
Lecturer
C.U.Shah College Of Engineering And Technology
Taught MicroProcessor and Digital Signal Processing to final year and 3rd year students.
Feb 2000 - May 2000
Lecturer
Sarvajanik College Of Engineering And Technology
Wroked as lecture and taught subjects like Microwave and Micro Processor
Aug 1999 - Jan 2000
Graduate Trainee
Larsen And Toubro Limited
1998 - 1999
~1 yr
Team & coworkers
Colleagues at Astera Labs
Other employees you can reach at asteralabs.com. View company contacts for 602 employees →
MM
Mason Mcguire
Colleague at Astera Labs
San Luis Obispo, California, United States, United States
View →
DM
Diego Morales
Colleague at Astera Labs
San Francisco Bay Area, United States
View →
AG
Aditya Guruprasad
Colleague at Astera Labs
San Francisco Bay Area, United States
View →
TW
Terence Wang
Colleague at Astera Labs
Taipei, Taipei City, Taiwan, Taiwan, Province Of China
View →
PL
Priscilla L.
Colleague at Astera Labs
United States, United States
View →
MS
Mackenzie Spykerman
Colleague at Astera Labs
Sunnyvale, California, United States, United States
View →
RL
Robert L.
Colleague at Astera Labs
San Jose, California, United States, United States
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WC
Will Chai
Colleague at Astera Labs
Shanghai, China, China
View →
HV
Hemant Vinchure
Colleague at Astera Labs
San Jose, California, United States, United States
View →
AH
Albert H.
Colleague at Astera Labs
San Francisco Bay Area, United States
View →
Mason Mcguire
Colleague at Astera Labs
San Luis Obispo, California, United States, United States
View →
DM
Diego Morales
Colleague at Astera Labs
San Francisco Bay Area, United States
View →
AG
Aditya Guruprasad
Colleague at Astera Labs
San Francisco Bay Area, United States
View →
TW
Terence Wang
Colleague at Astera Labs
Taipei, Taipei City, Taiwan, Taiwan, Province Of China
View →
PL
Priscilla L.
Colleague at Astera Labs
United States, United States
View →
MS
Mackenzie Spykerman
Colleague at Astera Labs
Sunnyvale, California, United States, United States
View →
RL
Robert L.
Colleague at Astera Labs
San Jose, California, United States, United States
View →
WC
Will Chai
Colleague at Astera Labs
Shanghai, China, China
View →
HV
Hemant Vinchure
Colleague at Astera Labs
San Jose, California, United States, United States
View →
AH
Albert H.
Colleague at Astera Labs
San Francisco Bay Area, United States
View →
3 education records
Shailesh Dave education
C.A.P.M, Project Management
Boston University Corporate Education Center
Electronics Engineering, Electronics
L.D. College Of Engineering
Diploma, Electornics & Communication
Goverment Polytechnic, Surat
FAQ
Frequently asked questions about Shailesh Dave
Quick answers generated from the profile data available on this page.
What company does Shailesh Dave work for?
Shailesh Dave works for Astera Labs.
What is Shailesh Dave's role at Astera Labs?
Shailesh Dave is listed as Sr Director ASIC Verification at Astera Labs.
What is Shailesh Dave's email address?
AeroLeads has found 1 work email signal at @asteralabs.com for Shailesh Dave at Astera Labs.
What is Shailesh Dave's phone number?
AeroLeads has found 1 phone signal(s) with area code 669 for Shailesh Dave at Astera Labs.
Where is Shailesh Dave based?
Shailesh Dave is based in Fremont, California, United States while working with Astera Labs.
What companies has Shailesh Dave worked for?
Shailesh Dave has worked for Astera Labs, Amd Pensando, Quantenna Communications, Netronome, and Einfochips.
Who are Shailesh Dave's colleagues at Astera Labs?
Shailesh Dave's colleagues at Astera Labs include Mason Mcguire, Diego Morales, Aditya Guruprasad, Terence Wang, and Priscilla L..
How can I contact Shailesh Dave?
You can use AeroLeads to view verified contact signals for Shailesh Dave at Astera Labs, including work email, phone, and LinkedIn data when available.
What schools did Shailesh Dave attend?
Shailesh Dave holds C.A.P.M, Project Management from Boston University Corporate Education Center.
What skills is Shailesh Dave known for?
Shailesh Dave is listed with skills including Verilog, Asic, Functional Verification, Systemverilog, Soc, Fpga, Debugging, and Uvm.
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