- Working on Test Development for Wafer-Level Sort and Package-Level testing of logic and memory products fabricated using Intel's latest manufacturing technology process node with Intel Foundry Services group.- Worked on R&D of next generation memory technology (3D XPoint) with Intel's Non-Volatile Memory Solutions Group.- Responsible for wafer-level test development as a part of Sort team. It includes developing test flows in C++, generating patterns to communicate with the device and logging and validating the results of the tests to check the performance of the device. Also involved in debugging/troubleshooting the device testing using waveform analyzers.- Working on testing the reliability of the device on a wafer-level by developing tests for checking the failure mechanisms. Developing stress tests that rigorously cycle the array at high temperature and then check for the bit error rates, data retention rates and any other impacts to the memory.- Responsible for carrying out engineering runs on wafers and packaged parts using memory testers in a pre-production environment for R&D. Also involved in facilitating the Fab in carrying out production runs.- Skills involved are C++, Semiconductor Device Physics, Digital Logic and Version Control for maintaining a large code base.

- Responsible for the safety analyses of various Systems, SW and HW-level work products in the ADAS project.- Includes analyzing mechanizations, schematics of systems and C/C++ code analysis. - Involves in-depth analysis of various microprocessors/microcontrollers for safe implementation of functionalities in the system and introduce/verify SW safety features.- Ensure safety of critical messages between microcontrollers through CAN and SPI communication protocols.

- Developed GUI for testing and monitoring of 400G optical modules using a control card. Developed two different GUIs - in C for Windows (using CVI LabWindows) and in Python. - Programming the FPGAs and Microcontrollers using Vivado Design Suite and testing the functionality of the devices.- Functional testing and troubleshooting of Dual Control Amplifiers, 100G Transponders, 400G Line and Client Cards, CM8 Controllers. Troubleshooting involved modifying the FPGA code, changing/designing test sequences using TestStand.- Careful analysis of schematics and PCB using Allegro Physical Viewer tool and ensure its correctness using various lab test equipment.

- Have been trained in UNIX, C++ and Oracle technologies.- Project in software development.- Also worked in software infrastructure domain with Windows team for application packaging and deployment.