Siew Weng Lee Email and Phone Number

Product Marketing/Management/DevelopmentResponsible for product roadmaps for multiple RF (radio frequency) CMOS process solutions for 90nm, 0.18 and 0.25 technology nodes, developing strategy in SOC or standalone RF, study RF market trends and develop "go-to-market" plans for each technologyDefine new RF process development (32nm and 45nm low power (LP) process) with Technology Development team. Justifying to upper management on new RF process development investments, and managing team (includes Technology Development, Process Integration) to project completionPromote RF CMOS process solutions to RF customers providing wireless solutions, namely in the areas of Wi-Fi, WiMax, wired ethernet, bluetooth ROI studies to determine feasibility of new RF process solution, inclusive of working on pricing strategies with Pricing teamPlan budget for RF IP, design enablement tools Product Training to RegionProvide RF process solution training for the sales and field engineering team, including authoring sales kit and conducting technical field-training.Customer RelationshipConduct sales presentation to customers on RF process solution offeringsInterface with customers on design requirements and work with technology, design services and process team to provide viable solutionWork with sales and field engineering team to ensure timely and effective support for key customersAchievements:Successfully launched new RF process solution on 0.18um node into the marketplace to replace existing product, and effectively increasing active customer engagement from 1 to 10+ customersSuccessfully brought Chartered's first 65nm LP RF customer to product prototype successSuccessfully completed first phase of product definition for 32nm and 45nm LP RF Identified key markets, developed market plans and sales kits to build awareness of RF product solutions. Effectively supported sales oriented activities to increase general interest in RF process in

0.35um mixed signal IC design projectLayout implementation and automationPDK developmentR&D work for radio frequency (RF) & DC Modeling/characterizationDeveloped optimization methodology for RF Inductors IPs for 0.25, 0.35um process based on customer specificationsRF modeling of passive devices - RF resistors, MIM, MOM, inductorsDevice mismatch modeling/characterizationDesign of RF Test-chip layoutTest-chip layout for RF CMOS 0.18, 0.25 and 0.35um CMOS processes for RF inductors, MOS/PN varactors and MOM capacitorsAchievements:Successfully developed optimization methodology for RF Inductors IPs to extend usability of spice modelsCompleted RF test-chip and modeling projects for 0.25 and 0.35um successfully to offer comprehensive solution for RF process

Project-in-charge for flicker noise characterization projects Direct Liaison with customer on project execution RF & DC Modeling/characterization RF modeling of passive devices including resistors, MIM, MOM, inductorsWorking with customers to ensure timely delivery and model accuracyDC modeling of transistors using BSIM3v3 modelsFlicker noise measurement and modeling Design of RF Test-chip layoutTest-chip layout for RF CMOS 0.13 and 0.18um process for inductors/res/MIM/MOS, PN varactors for major foundriesAchievements:Successfully completed RF test-chip and modeling projects for 0.13 and 0.18um process, delivered high quality models within ±5% error figures

Wafer level reliability control (WLRC)Pioneered the WLRC program for product engineering group in accelerated testing including electromigration, GOI Parametric (Etest) analysis of product functional/electrical failuresIdentify electrical failure mechanisms - include transistor failures, change in material characteristics, leakage and process marginality failures.Involved in developing parametric/electrical test programs on Agilent HP4156C/HP4284A and Keithley platforms. Bench testing and characterization on HP4156C/HP4284A.Involve in yield enhancement quality improvement teamsDeveloped technique to identify process issues using parametric dataConducted training of technique to fab process engineers to speed up analysis processWorked with process integration and QC in yield improvement taskforce to provide analysis for marginal product failures and backend failures, identify root cause processes to reduce product fallout.Spearheaded new product checkouts and yield improvement projectSpearheaded new memory devices product checkoutAchievementsSuccessfully developed novel methodology of using electrical data in root cause analysis to identify zero/low yield wafer issues (~25% of zero yield issues), providing effective and timely feedback for process integration team. Completed transfer of new memory product device checkout from Micron and managed yield programs till probe yield reach about 90%Successfully implemented and automated WLRC (wafer level reliability control) program for early detection of process reliability issuesCompleted parametric (E-test) test development for new product checkout

In charge of Thin Film Metal Deposition CVD processPrimary job involved new process recipe qualification, improvement of process robustness through DOE.Working with Process Integration to fine tune process, participating in defect reduction and yield improvement projects.Utilize SPC tools to aid in streamlining defect reduction efforts.Achievements:Successfully released process to production for CVD Tungsten process for 64 megabit DRAM processMaintained robustness of process through usage of SPC tools and process DOESuccessfully worked with PI team to fine-tune process (contact loop) reliability to reduce potential device fallout