Sushil Kumar Email & Phone Number

I am motivated and enthusiastic FPGA/ASIC Design Engineer having 2.5+ year of overall experience.Language : Verilog, VHDL, C, C++.Tools : ISE Navigator 14.7, Xilinx Vivado 2022.1, Cadence Ncsim, Cadence Genus(Legacy Mode), Cadence Jasper Gold Superlint and CDC Verification app, Cadence OrCAD for PCB design, Putty (SSH and Serial Communication), Tera term, WinScp.FPGA boards handson like Nexys Artix 7, Basys 3 and Zynq Ultrascale Mpsoc Zc104,Embedded Boards Handson : BeagleBone Black Board.Skills: Amba protocols : [APB,AHB,AXI], I2C ,SPI, UART, RTL Debugging, SOC RTL Integration, TCL Scripting, CDC and linting, Constraining the design, low power synthesis, Circuit Design, Schematics Capture, Layout design, Gerber file generation.