3+ year experience in ASIC Physical Design and Automation.Good understanding in the fundamentals of CMOS.Knowledge in the Digital Design Concepts and Basic Electronics.Experience in cut edge technologies including 7nm, 5nm.Good understanding in Statistical Timing Analysis, On-Chip Variations and Timing Parameters.Good knowledge in ASIC Physical Design (RTL to GDS flow)Proficient in complete ASIC backend flow including Synthesis, Block level and Top/Hierarchical Floorplan, Full Chip Power and Bump Planning, PnR, Analog IP integration, STA and Sign-off, PV, FM etc.Good understanding and experience in Analog IP integration such as PLL, SerDes, etc.Experience in training new team members in Top-Level PD/STA and Hard IP Block closure.Automation experience including ownership of ASIC Flow from Synthesis to Sign-off.Post-Silicon Timing analysis and review, silicon-freeze manual ECOScripting languages: Python, TCL, ShellEDA Tools: HSPICE, Custom Designer, VCS, Design Compiler, IC Compiler, Fusion Compiler, PrimeTime, Innovus, Tempus, CalibreExperience with Cadence and Synopsys tools