Raj Thakkar Email & Phone Number

Austin, Tx, Us

San Jose, California, United States

Skills: SystemVerilog · Simvision · Genus Synthesis · Assertion Based Verification · I2C · Verilog• Performing Frontend Design & Verification, by fixing Lint & CDC, RDC errors of the components; also synthesizing & optimizing designs metrics such as area, power & performance. Finally, executing Static Timing Analysis (Setup & Hold) for the timing closure in front-end.• Transforming a Tristate-bus into a MUX-bus to drastically enhance bus bandwidth efficiency, thereby mitigating in-line delays & congestions.• Incorporating existing IP into an new data-bus on a (TSMC-N5) 5nm technology node, conducting test cases by increasing data rates & clock frequency from 640Mhz to 1.2Ghz to address potential bottlenecks using Synopsys Fusion Compiler tool.

• Implemented signal processing kernels to run on novel systolic array processor, integrating a Python-based Manager script for data flow.• Developed generalized data flows, code templates & Verilog testbenches of various kernels for behavioral & functional simulation.• Worked on timing estimation & data mapping of various kernels such as FIR, FFT, OFDM, QPSK & components of demodulation blocks based on VLIWarchitecture for high degree of pipelining & highly synchronized multiprocessing and verify using API on FPGA.

Spring 20231) EEE202- Circuits 1 2) EEE554- Random Signal Theory and ProbabilityFall 20233) EEE541- Electromagnetic Fields and Guided Waves4) EEE598- RF Transmitters and AmplifiersSpring 20245) EEE531-Semiconductor Device Theory

• Familiar with all the stages in Physical design including Floor Planning, Placement, CTS, Routing, Physical Verification (DRC & LVS).• Utilized Synopsys ICC2 for macro placement with fly lines, designed a robust power network to prevent floating pins & meet IR drop targets.• Exposure to Primetime tool for Static timing analysis (Timing Path, Timing Arc) & fixing timing closures (Setup & Hold) on 28nm technology.• Implemented timing driven Placement by minimizing congestion and applying Placement blockages.• Handled design of a balanced Clock tree, Clock Domain Crossing & optimized the Skew. Utilized TCL to automate Physical Design process.

Master Of Science With Thesis, Computer Engineering (Electrical Engineering)

EEE 525: VLSI Design CSE 520: Computer Architecture II CSE 551: Foundations of Algorithms EEE 591: Digital Systems Circuits EEE 554.

Bachelor Of Engineering - Be, Electronics And Telecommunication, 9.11/10.0

Activities and Societies: Active member of IEEE Student Chapter >IEEE RAIT Student Chapter GENERAL SECRETARY -2021