Senior Component Design Engineer
CurrentSenior Component Design Engineer with 21 years experience working on leading edge CMOS designs incorporating high performance, low power solutions with multiple processes. Physical technical lead for the PEG IWG projects. Responsible for the review of the floorplanning generation, placement, timing closure eco, physical LV verification, packaging and the overall sign off of the PEG IWG projects to the foundry. Resolving technical issues with the foundry directly. I have a 100% success rate in projects working first time.Expertise as follows:Extremely proficient in various P&R tools e.g. ICC, Magma, Encounter, Blastrail.Excellent working knowledge of Physical Verification tools Calibre, ICV and PVS.Extremely proficient in all aspects of Analog and RF Layout techniques.Highly proficient in use of Virtuoso Layout Editor and Calibredrv.Experience working with Mask and Fabrication (TSMC) engineers. Main point of contact between packaging houses and team to develop WLCSP, ETCSP and FCBGA solutions. Good working knowledge in Front End Design Process.Excellent Management/Mentoring skills.Excellent interpersonal skills participating in global conference calls and meetings.Excellent working knowledge of Scheduling and Project planning.Experienced member of Inhouse Advanced Training Team and Quality Awareness Team.