Thomas H. Email and Phone Number

Formed a team and led development of the next-generation coherent links cycle-approximate performance model and projections methodologies, resulting in several major performance enhancements within the link, on-die interconnect, and coherence protocol. Active contributor to improving and enhancing prior generation models, projections/methodologies, and CPU performance.

Lead Performance Architect for the second-generation Omni-Path Host/Fabric Interface (HFI).Formed a team and led development of the second-generation Omni-Path Host/Fabric Interface cycle-approximate performance model, a novel integrated network interface targeting exascale HPC and datacenter applications. Optimized several aspects of the microarchitecture and coherence protocol. Developed workloads, created projections, and tracked milestones. Worked with worldwide teams to resolve modeling, integration, and conceptual issues.

In this role, my main focus was power, with some nifty CPU performance enhancement - this was a very busy 18 months. I developed novel power management IP that increased resiliency and efficiency. I prototyped implementations within performance/power models and guided design, firmware, and validation engineers through product implementation. I authored and maintained architectural specifications for SOC subsystems, and worked with SOC architecture to include platform hooks for new power management features. And I built the CPU performance measurement methodology for Quark.

Remarkably bland title for my responsibilities as SW Lead Engineer within the Atom architecture group, which include radically improving the performance of present and future software (operating systems, libraries, drivers, applications, tools, etc) on today's platforms, as well as performing deep competitive analysis and improving future generations of Atom and derivative SoCs.

This is the continuation of my position at Intel, post-acquisition by Marvell, focusing primarily on imaging (research and development, C++ algorithmic modeling, microarchitecture, and SoC performance analysis), with some further security work improving modeling of dynamic and static hardware failure and the analysis of the recovery algorithm's robustness for a hardened crypto engine.

Developed the integrated compiler, simulator, and debugger for an embeddable cryptographic engine, after which I joined the XScale microarchitecture team.