Benjamin Ting is a Principal Engineer at Microsoft. He possess expertise in systemverilog, verilog, fpga, soc, functional verification and 11 more skills. Colleagues describe him as "With my background in mixed signal verification, it will be helpful to understand how digital methodology works and be able to handle it when it needs. Before taking Mr. Ting’s class, I had a short UVM training from a training company. But it did not help much, feeling the complicated UVM confused. While Professor Ting’s class is much more different. It reinforces learning by repetition and develops test cases from scratch in well-designed homework. Its final project was about an entire UVM testbench from scratch, included all UVM components plus SVA and functional coverage. Professor’s teaching method, class duration of 10-week plus labs, and interactive class are a good combination to learn UVM material. It helped me to have more in depth understanding of UVM. I enjoyed his professional but fun class." and "Before taking Benjamin's class, I had corporate UVM training of 1 and few days. I also have industrial experience in SV and UVM. I wanted to sharpen my skill and have expert view and advice to write testbench (TB ) such that it is easy to maintain and to refactor. Benjamin reinforces learning by repetition and develops TB from scratch. Benjamin's teaching method, class duration of 10-week plus labs, and interactive class are good combinations to learn UVM material. He helped me to have more in depth understanding of UVM. Our final project was writing the entire TB from scratch included all UVM components plus SVA and functional coverage. I'm glad attending his fun class."