With over 10 years of experience in FPGA/ Digital Design roles. I am passionate in RTL coding, Synthesis, IP integration for digital design and Formal Verification of Communication protocols like AXI, PCI, Ethernet and applying System Verilog assertions to complex verification problems. I hold a PhD in FPGA implementation and Design of signal processing architecture Nirma University, and MTech in digital electronics from Manipal Institute of Technology. I have also worked on Formal verification techniques and applied it to high speed IPs viz. AMBA, PCI, Ethernet. I have been using system Verilog assertions both in functional and formal verification at every level.