Venus Patel Email & Phone Number

- Worked as a Verification Environment Engineer for GFX Hardware team and managing several pre-silicon validation areas such as owning the development and maintenance of System Verilog/UVM based behavioral libraries and portions of the test bench.- Worked on the development of verification plans with respect to the validation environment and modifying the libraries..- Was Part of the team that is facilitating the verification environment in our IP to advanced UVM. Worked on behavioral libraries as per the IP requirements and protocols from the UVM base libraries that all validation clusters in current IP would use as their verification environment. - Worked on self-testing environment (block/unit level tests) for the Validation Environment (Time Efficient) that will run the simulation and debugging actual design flaws and environment issues. OOP programming - C++, Perl, Python, System Verilog.- Worked with multiple scoreboards to implement and improve the monitors and trackers methodology with Intel specific tool that are efficient and helps to improve the validation flow and help the debug process. - Built and maintained the verification test bench components and environments which includes writing random/constrained based and injection based verification sequences, assertions as well as test writing using UVM.- Experience in Code coverage and Functional coverage points that helps to improve test environment to target the validation coverage holes- Developed/Maintained the other Intel specific TFMs and automations used for Validation in our IP that improves our quality and throughput or our IP. These tools are generally Perl, C++ based tools.

Master Of Science (Ms), Electrical And Electronics Engineering

Bachelor Of Engineering (Be), Electrical Engineer