Working on the Server Platform Validation Team to support IO.

Production wafer sort, package test, and split lot characterization test development on Credence Sapphire and Verigy 93K test platforms for PCIe & DisplayPort IO. Develop and document improvements for back-end data processing tools.

-- Texas Instruments support for ATE hardware and software development in C++ for final test production solutions on Eagle 364 platform. Conversion from legacy test platforms included optimization and characterization across temperature using Multi-Test MT9918 handlers. Testing of LED drivers using I2C communications. Op-amp testing, DAC and ADC test conversions from HP94K to ETS-364. Statistical data analysis including histograms, trend plots, %GRR.-- AMD support for Credence Sapphire test development using XML and XTOS. Perl scripting for pattern generation.

Assisted the research and development phase for a DSP-based data acquisition system. Design tasks included writing specification documentation, component selection tradeoffs for ADC, processor and memory storage architecture, and long-range wireless network communications. Condition-based monitoring system demonstrated with proprietary algorithms modeled in National Instruments’ LabVIEW. This is a startup environment targeting solar and wind energy markets.

See Eagle Test description. This new position was created due to TER acquisition of EGLT in November 2008.

I was responsible for designing, developing and debugging ATE hardware and software for a strategic, competitive project. The device under test (DUT) was a 100-pin semiconductor device, an automotive power control unit (PCU) for anti-lock braking systems (ABS). I was technical lead for a team of engineers for one year, developing a quad-site application using the ETS-600 tester docked to a Delta Castle handler. This allowed us to refine the program across cold, hot and room temperatures in preparation for the production environment. We optimized the customer’s existing test solution by over 50% through improvements in coding techniques, and by advancing the design of our system architecture and software.• Mixed signal testing including design of coherent analog waveforms, digital patterns, and timing generation• Extensive use of the Eagle ETS-364 and ETS-600 platforms and instrumentation• Trained on Raptor software environment, which applies to the ETS-200T for wafer sort and the ETS-200FT for final test of discrete MOSFET devices on index-parallel turret handlers• Gauge Repeatability and Reproducibility (GRR) data collection and processing using Data Power and analysis of variance (ANOVA)• Mentor Graphics Design (schematic) Capture (WG2005)• Simulation of analog circuits using Linear Technology Switcher CAD• Microsoft Project• Microsoft Excel• Microsoft Visual Studio 2005 programming, debug and compiling environment for Eagle Vision• C++

In this role I helped manage our workflow between the factory and the field, clarifying specifications and requirements on the front-end of the quoting process, so that when the job was booked we had minimal delays due to technical questions. I also guided our factory engineering group through a major transition to drive the documentation process for our primary customer. I personally reviewed most of the critical board designs in a live session with the customer so that we could address and document their concerns in real time and respond quickly. This position involved a certain amount of travel to customer sites to assist in winning new business, or to support existing business groups.• Hardware support for ATE customer tester platforms including Teradyne, Eagle, LTX. • Mentor Graphics Expedition training for PCB layout and schematic capture.• Sales quotation technical support involving specifications of boards and contactors relative to signal speed requirements and board material.

The ATE applications role includes both strategic and ongoing support for customers in the development cycle for new silicon. I helped the customer develop their hardware design, test program, and debug of first silicon at wafer probe and package test. The test techniques included mixed-signal and digital test patterns, analog waveforms, and timing generation to stimulate the device under test (DUT). Over these five years I became seasoned by having direct exposure to customers, which required the ability to demonstrate functional tests, mentor about methods, and handle high stress situations. In a strategic competition for gaining market share, I was involved in production ramp for ADSL devices overseas for one month, troubleshooting hardware and yield issues. This project drove several new tester sales. • UNIX skills, primarily for Sun Solaris• Extensive use of the Fusion HF/HFi platform and its instrumentation• Perl scripting for converting patterns to enVision language elements• Schematic capture using Veribest98, Mentor Graphics tools

My first engineering position allowed significant growth and exposure to several different areas of hardware and software design. I took over a board design from another engineer who left the company within two months of my arrival. I started with his block diagram and a handful of datasheets for components he recommended, and built the system from there. The system was a VME card cage which included several other COTS (commercial off the shelf) boards, the main board being a Motorola card whose embedded software and drivers were developed by the others on my team. We had to coordinate the handshaking VME protocol between the driver and my board’s memory interface (a dual-port RAM). I also had to learn how to control and filter bi-directional analog data being clocked by audio codecs to and from the DSP. This involved memory mapping, bus architecture design, and optimization.• Schematic capture using Cadence Concept, netlist generation and PCB layout review in Allegro• Simulating DSP algorithms in MATLAB with C implementation for 16-bit linear audio• Code Composer firmware development for Texas Instruments’ TMS320C6201 DSP• C and assembly language software optimization techniques• Algorithm development for decimation and interpolation, FIR filtering, and PCM u-law conversion• Altera programmable logic design (PLD) using In System Programmability with JTAG• Simulation of digital design using schematic graphical entry and AHDL with Max Plus II• Designing interfaces for UART, audio codec, FIFO memory, DPRAM, RS422, and PGA devices