Undergraduate Researcher
As part of the Summer Undergraduate Research Fellowship, I worked with Purdue University's SoCET team to optimize vector memory accesses in a RISC-V processor. Initially, the vector processor serialized memory accesses between all four vector lanes and the L1 data cache could only read & write 32-bit words. My changes to the core coalesced memory accesses between lanes that would point to the same cache block & matched tags with each other, and added read & write data lanes the width of a cache block between the load-store controller & the L1 data cache. The open-source tools Verilator and GTKWave were used to simulate and verify waveforms, respectively. Simulations showed an average 1.25 times speedup comparing the coalescer design to the of the serializer using a custom suite of benchmarks. Synthesis of my design involved Cadence's Genus and SkyWater's PDK. Addition of the coalescer did not impact the processor's critical path.I also became experienced with the engineering research process. My responsibilities included reading & annotating literature, writing an abstract & technical summary, and presenting my work at the end of the summer.SURF and SCALE funded this experience.