Product Development Engineer
Current• Responsible for pre silicon and post silicon validation of 3DXP memory IO (DDR spec) circuits for multiple products.• Led successful power on for 3DXP IO circuit followed by characterization across PVT corners and volume data analysis.• Supported customer returns/system failures, root caused and delivered solutions by working in close collaboration with multi-functional teams to drive test hole closure.• Developed and debugged complex test methods on Advantest V93K tester platform using C++ on SMT OS.• Generated Perl based data analysis scripts and used JMP/Excel for volume data analysis and visualization to evaluate device performance and margin to spec.• Collaborated with cross-functional teams within Intel to define test plans for Analog IP’s (HSIO, DDR, PLL).• Owned and debugged issues during different silicon stages from pre-silicon, bring up, validation and production phases of SoC programs.• Supported teams in Design, Dfx. and Software to ensure first silicon readiness, IP functionality enablement and debug of critical features.• Developed a Python based GUI tool to gain data insights, effective yield and parametric analysis supporting multiple projects and configurable for future support.