2015-present: Chip architect and engineering manager within ADI’s Transceivers Product Group. Primary responsibilities include leading the definition of the chip architecture and requirements for ADI’s frequency agile RF transceiver products.2001-2014: IC Designer. Key contributor to the development of ADI’s wireless transceiver products, including the Othello TD-SCDMA handset TX, the AD9354 (an RF-to-bits WiMAX TRX), the AD9361 (a frequency agile ZIF RF-to-bits TRX tuning from 70MHz to 6GHz), and the AD9371 (world’s first integrated ZIF transceiver for multi-carrier cellular base stations). Responsibilities included architecture selection; chip level impairment budgeting; circuit design, verification, and layout; definition of digital hardware and algorithms for block and system level calibrations; chip evaluation and debug. Designed circuits such as LNAs, upconverters, variable gain amplifiers, passive mixers, frequency dividers, LO generation and distribution, phase detectors, tunable opamp-RC filters, comparators, current steering DACs, and bandgap references. Contributed to the design and debug of RF PLLs, VCOs, DACs, ADCs, and the transceiver digital signal paths.

IC Designer, High Speed Converters group, designing CMOS pipeline ADCs for video applications.