Jonathan Rodriguez Email & Phone Number

Sugar Land, Texas, United States

Richardson, Texas, United States

Wrote Verilog code for a test-chip, which consisted of a series of sub-circuits from the customer, as well as the interconnect, tying all sub-circuits to create the test-chip.Wrote Verilog testbenches to simulate the sub-circuits against a series of stimuli, depending on whether the sub-circuit is combinational or sequential.Wrote a Verilog testbench to test the interconnect, which consisted of randomizing the address bits, given that each sub-circuit is defined by a particular address.Suggested the client to redefine the Scan implementation, from a long Scan chain into a series of shorter Scan chains, later multiplexed, to avoid timing violations.Ran synthesis using Cadence Genus, which converted the written RTL code into a gate-level netlist used later for place-and-route.Wrote Skill scripts to automate device generation, which took customer-provided specs from Excel and parsed them to change device sizing or changed other device attributes.Wrote Skill scripts to automate placement and routing of test-chips by calling device instances from a standard cell library, then routing them programmatically.Ran Design Rule Checks (DRCs) after completion of layout design to ensure all physical properties own the test-chip layouts adhere to customer requirements.Scheduled weekly meetings with client representatives to sync up on progress and define next steps, depending on customer feedback.Completed over 200 test-chip layout designs by use of automation tools, as well as manual effort in the case where automation is time-consuming or impractical.

Dallas/Fort Worth Area

Worked with the Systems Health team by analyzing flight data to isolate severe faults, based on fault occurrence data, mission logs, and recommendations from the Test Conductors.Read and archived mission logs to identify whether radar tests were done, as well as documented resolutions from existing faults, which saved days to weeks of triage time.Ran Analog-Digital-Optical boards through a Specialized Test Equipment to ensure signals meet required thresholds, while performed action items to distinguish the root cause between faulty hardware, ports, or wiring.Documented defects and work arising notifications, which would be directed to the Test Manager, who would determine whether the ADO boards and be fixed in-house or sent to an external shop.Signed off four ADO boards after board-level testing, declaring the ADO boards ready for system-level testing on aircraft.

Dallas/Fort Worth Area

Ran MathCad to simulate Phase-Locked Loop (PLL) behavior, given a list of different crystal oscillators used in previous projects.Compared MathCad simulations against LTSPICE simulations to ensure accuracy between theoretical and practical applications.Created Printed Circuit Board (PCB) schematics and layouts using Mentor Graphics tools as a pilot project from the Mixer team in developing PCB layouts in-house, as opposed to through an external vendor.Identified a list of parts used on existing mixer devices, which involved using PLM Windchill to catalog parts based on version and cost, which helped create a preliminary Bill of Materials (BOM) for upcoming products.Coordinated with parts vendors, which confirmed the specs for their products, as well as guided the mixer team to other devices, in the case of device obsolescence.

Hillsboro Or

Designed and developed digital circuits, which would eventually go into Intel's Tiger Lake processor products.Worked with the backend team in the Devices Development Group (DDG) in synthesizing RTL from the front-end team, then running Synopsys ICC2 to create physical designs for tape-in.Performed synthesis using Synopsys Design Compiler to take in RTL, as well as timing constraints and overrides to convert the provided RTL into a gate-level netlist. Coordinated with RTL owners in identifying false paths, which led to writing false paths and other timing constraints in Tcl to prevent false timing violations later on.Wrote Tcl scripts to create Engineering Change Orders (ECOs) by modifying logic in the case of major RTL changes, assuming re-synthesis isn’t feasible.Worked with the Timing team and RTL owner in defining clock-crossing overrides in Tcl or add additional logic, specifically when transitioning from a fast clock to a slow clock.Performed place-and-route by using IC Compiler to convert the existing netlist into a GDS file, which would be used during fabrication. Ran Functional Equivalence Verification (FEV) tools to ensure logical equivalence between the gate-level netlist and GDS file, once place-and-route was finished.Worked with the Layout and Timing teams to ensure all timing paths are met, which included changes to device placement to minimize wire length or leave room for buffer placement.Collaborated with the Quality Subject Matter Expert (SME) in isolating real violations, such as timing or logical violations, from non-serious violations, as well as defining waivers, based on previous projects and recommendations from other SME’s.Submitted two designs for tape-in after running sign-off flows and consulting with multiple SME’s, ensuring the design is satisfied in the pre-silicon domain.

Dallas/Fort Worth Area

Contributed towards designing an automated data extraction applet to utilize the SCADA network linked between wind turbines and the corporate database. Compiled online event occurrence reports to record major component failures, based on data given by the Operations team and any downtime recorded.Wrote SQL queries to validate alarm accuracy by comparing raw alarm data against data provided by Operations management, thus filtering out false alarms.Developed C# applets to simplify the extraction of raw alarm data into a simple interface, to where non-engineers find ease of use.

Master Of Science - Ms, Electrical And Electronics Engineering, 3.85

Bachelor'S Degree, Electrical Engineering

Activities and Societies: Society of Hispanic Professional Engineers, Quest Scholars Network

Diploma