Mayank Pachauri Email & Phone Number

Hathras, Up, In

Nit Trichy

Nit Trichy

Working as the Deputy Manager of the Organizing Committee Team for Currents, the National-level Technical Symposium at NIT Trichy's Department of Electrical and Electronic Engineering.

Nit Trichy

As the Coordinator of the Organizing Committee Team for Currents, the National-level Technical Symposium at NIT Trichy's Department of Electrical and Electronic Engineering, I effectively participated in diverse tasks encompassing event planning and coordination. This position empowered me to refine my leadership abilities, decision-making skills and acquire invaluable expertise in event management.

Gandhinagar, Gujarat, India

Involved in a research project focused on the Analysis of Digital SRAM-based In-Memory Computation (IMC). Simulated Bit-Parallel architecture-based compute logic for IMC using Cadence Virtuoso and conducted a performance analysis, comparing the speed and energy consumption with Bit-serial architecture-based compute logic for the same SRAM array size.

Varanasi, Uttar Pradesh, India

During my internship, I was actively involved in a project focused on Device circuit co-design for non-volatile latch using Ferroelectric FET (FeFET). This experience afforded me the opportunity to design and simulate range of non-volatile memory circuit designs, including PCSA Latch, FeRAM, SR Latch, and SRAM, by leveraging Ferroelectric FETs (FeFET) in HSPICE. Through this opportunity, I gained a comprehensive understanding of circuit design, and troubleshooting techniques concepts and acquired valuable hands-on experience in their application.

Bachelor Of Technology - Btech, Electrical And Electronics Engineering

Cbse 12Th, Science, 92.2%

Cbse 10Th, 95%