Mitul Modi Email & Phone Number

Chandler, Az

Lead definition of the Client Segment (>$8B quarterly revenue) product package architectures by integrating customer performance, system, and cost requirements, advanced packaging technologies, electrical specifications, system thermals, manufacturing, and reliability. Noteable technology achievements include architecting the industry’s first Foveros 3D logic-on-logic System on a Chip (Lakefield) and Intel’s first discrete graphics product (ARC).Lead the Semiconductor Packaging factory of the future definition for high-cost geographies including process, equipment, and labor cost reduction strategies, innovation in factory automation, and environmental sustainability programs for semiconductor materials, processes, and factory layout.

Lead the Package Architecture and Assembly Process Co-design for new or disruptive microelectronic assembly programs. Responsible for initiating new equipment selection where process gaps exist and leading process development to establish a manufacturing baseline. A key achievement was the definition and development of Intel's first ultra-thin and low-cost wirebond stacked hybrid flip-chip product XG736, which appeared in the iPhone 7. Continued to secure volume for three generations of the product by advancing the packaging technology offering.Secured >60 Mu of new business volume for Intel’s Custom Foundry by marketing Intel’s assembly technical leadership and driving cost reduction through continuous benchmarking to Outsourced Semiconductor Assembly and Test (OSAT) and other competing foundries.

Serve as the Microelectronic Component FLI (First Level Interconnect) Architect for proof-of-concept and disruptive technology platforms that achieve Moore's law scaling, aggressive cost reduction, and significant leaps in component performance. Responsible for driving cross-organizational, multi-disciplinary teams to execute modeling, small-scale assembly experiments, lab-scale evaluations, supplier capability assessments, and financial analyses. A key achievement was the delivery of a technology that reduced Interlayer Dielectric stress by 35%, providing a path for greater margin in silicon to package assembly.

Managed a 5 person team responsible for forecasting and finding solution to mechanics related gaps in Silicon Sort and Final Component Test. Some key highlights include: 1) establishing the Intel first ever Sort Probe fundamental failure mechanism characterization and mechanics/materials based design rules and 2) delivery of a Back End Test Finite Element model automation, reducing the time for Back End test to minutes and ensuring consistency across analysts.

Senior engineer responsible for delivering technical contributions in the area of materials development and structural mechanics for Intel CPU/Chipset Research and Development programs. • Managed Assembly and Test Technology Division’s research deliverables. Defined the structural mechanics technology roadmap for Intel’s products 4-5 years from HVM. Drove solution to the roadmap gaps and made substantial technical contributions through innovation in areas of low-k dielectric fracture, product assembly, mechanical reliability, and cost reduction through material optimization. • Delivered the Mechanical Technology Performance Specification to achieve technical certification for over 8 Intel product platforms. Meeting these deliverables was achieved through a self-managed program using modeling and experiments to define the performance envelope in the areas of shock/drop, temperature cycling, and other custom use conditions which may impact package mechanical reliability. • Expansive portfolio of technical contributions, many of which were “industry firsts”, in the application of finite-element and self-developed analytical approaches. Established organization-wide recognized content expertise in the areas of Micromechanics, Warpage Fundamentals, Solder Joint Reliability (shock and fatigue), and First Level Interconnect Assembly and Reliability.

Survivability Engineer, 1997-1998Test Lead for the Terrain Sensor Laboratory focused on development of terrain mapping for the Grizzly Countermine Vehicle. Responsibilities include test/experiment design, instrumentation installation, data acquisition, post-test data analysis, test software design/coding, and prototype design/development. Test and Simulation Engineer, 1996-1997Simulation Manager for the Grizzly countermine vehicle program. Responsibilities include management of simulation development, supervision of simulation execution, and integration of simulations into the program with the focus of augmenting testing and evaluation, support engineering design, and refining vehicle requirements.

Ph.D., Engineering - Solid Mechanics

Activities and Societies: President Microelectronics Packaging Research Center Student CouncilDesign, fabrication, and reliability.

M.S., Industrial Engineering

B.S., Mechanical Engineering