Sai Sruthi Ravilla
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Sai Sruthi Ravilla Email & Phone Number

Sr Product Development Engineer at AMD
Location: San Jose, California, United States 3 work roles 2 schools
1 work email found @marvell.com LinkedIn matched
✓ Verified Jul 2026 4 data sources Profile completeness 100%

Contact Signals · 1 work email

Work email s****@marvell.com
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Current company
AMD
Role
Sr Product Development Engineer
Location
San Jose, California, United States
Company size

Who is Sai Sruthi Ravilla? Overview

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Quick answer

Sai Sruthi Ravilla is listed as Sr Product Development Engineer at AMD, a with 16705 employees, based in San Jose, California, United States. AeroLeads shows a work email signal at marvell.com and a matched LinkedIn profile for Sai Sruthi Ravilla.

Sai Sruthi Ravilla previously worked as Senior Product Design Engineer at Western Digital and Post Silicon Validation Test Engineer at Marvell Semiconductor. Sai Sruthi Ravilla holds Master'S Degree, Computer Engineering, 3.30/4(Cgpa) from Arizona State University.

Company email context

Email format at AMD

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{first_initial}{last}@marvell.com
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AeroLeads found 1 current-domain work email signal for Sai Sruthi Ravilla. Compare company email patterns before reaching out.

Profile bio

About Sai Sruthi Ravilla

Sai Sruthi Ravilla is a Sr Product Development Engineer at AMD. They possess expertise in matlab, python, microsoft office, java, hardware architecture and 9 more skills.

Listed skills include Matlab, Python, Microsoft Office, Java, and 10 others.

Current workplace

Sai Sruthi Ravilla's current company

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AMD
Amd
Sr Product Development Engineer
santa clara, california, united states
Website
Employees
16705
AeroLeads page
3 roles

Sai Sruthi Ravilla work experience

A career timeline built from the work history available for this profile.

Sr Product Development Engineer

Current
Amd

Austin, Texas, United States

Aug 2023 - Present

Senior Product Design Engineer

*As a Post Silicon Validation Engineer I was responsible for collaborating with design/system teams to define and track characterization test plans through different stages of NAND memory development cycles from 1st silicon to mass production.*During this process I became familiar with ATE Teradyne memory testers and Advantest systems like Magnum EV1/EV2. Experienced with test development on these platforms.*Validated TRIMS on different generations of 3D NAND flash memory devices, Worked on Erase/Program/Read Algorithms and retrieving Current and Timing Specifications of the NAND device in DDR interface.*Performed Characterization with high speed testers to check different Analog, Logic, Core Characteristics of different generations of 3D NAND.*Developing test strategy and coverage for different customers, aligning test boundary conditions across different product requirements, data sheet specifications and PVT corners.*I have taken an initiative to work on developing different post processing scripts (in Python) which process the data that we collect after performing regression tests.*Also I was accountable for analyzing and preparing characterization reports, maintaining a database of statistical data and mask judge reports.*Experienced in working with cross functional teams design, device and system to develop and bring up the 3D NAND.*Performed Validation of custom design test sequences to support App Notes and System Engineering requirements.

Mar 2022 - Jul 2023

Post Silicon Validation Test Engineer

Chandler, Arizona, United States

*Providing validation support for Mixed signal Read Channel(RDC) IC blocks like PLL,Variable Gain Amplifier, ADC ,DAC etc.*Debugging and Customizing test coverage and defining test strategy when silicon issue is discovered.*Hands on experience with general lab equipment like Oscilloscopes,V/I source, waveform generators.*Familiar with basic HDD related concepts like Tracks, Zones, Servo, Data, preamble, Sync Mark etc.*Parsing High volumes of Data using tools like JMP14 to examine for any shift or jump in the expected results.*Developing support scripts/programs (using Python.) to run different test cases. Have an experience with Atlassian Software Tools.

Nov 2020 - Feb 2022
Team & coworkers

Colleagues at AMD

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2 education records

Sai Sruthi Ravilla education

Bachelor'S Degree, Electrical, Electronics And Communications Engineering, 8.63/10(Cgpa)

FAQ

Frequently asked questions about Sai Sruthi Ravilla

Quick answers generated from the profile data available on this page.

What company does Sai Sruthi Ravilla work for?

Sai Sruthi Ravilla works for AMD.

What is Sai Sruthi Ravilla's role at AMD?

Sai Sruthi Ravilla is listed as Sr Product Development Engineer at AMD.

What is Sai Sruthi Ravilla's email address?

AeroLeads has found 1 work email signal at @marvell.com for Sai Sruthi Ravilla at AMD.

Where is Sai Sruthi Ravilla based?

Sai Sruthi Ravilla is based in San Jose, California, United States while working with AMD.

What companies has Sai Sruthi Ravilla worked for?

Sai Sruthi Ravilla has worked for Amd, Western Digital, and Marvell Semiconductor.

Who are Sai Sruthi Ravilla's colleagues at AMD?

Sai Sruthi Ravilla's colleagues at AMD include Sian Guan Chan, Jerry (Yang) Yu, Mark Fuselier, Sisanda Ntsika, and Kavita Sharma.

How can I contact Sai Sruthi Ravilla?

You can use AeroLeads to view verified contact signals for Sai Sruthi Ravilla at AMD, including work email, phone, and LinkedIn data when available.

What schools did Sai Sruthi Ravilla attend?

Sai Sruthi Ravilla holds Master'S Degree, Computer Engineering, 3.30/4(Cgpa) from Arizona State University.

What skills is Sai Sruthi Ravilla known for?

Sai Sruthi Ravilla is listed with skills including Matlab, Python, Microsoft Office, Java, Hardware Architecture, Cadence Virtuoso, Computer Architecture, and Verilog.

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