Terry Riley Email and Phone Number

Research consultant in the Department of Molecular and Cell Biology designing and assembling an improved Surface Plasmon Resonance Imaging system.

Consultant on technical project defining state-of-the-art, generic logic process flows for use by small to medium sized semiconductor companies.

Worked within three diverse areas of next generation process development as member of the 65nm technology node team.Plasma-Enhanced Chemical Vapor Deposition (PECVD):Developed PECVD films for sidewall spacer deposition to replace older, low-pressure deposition processes. The new processes occur at lower temperatures, improving device performance and lowering manufacturing costs.Enhanced PECVD processes for S/D poly cap deposition, creating manufacturing flexibility in allowing processes to be fine-tuned for specific part being produced.Plasma Etch:Developed low defect count gate etch process by introducing new materials into manufacturing tool and adjusting etch process settings, decreasing defect count by 8x and more than doubling the number of sellable pieces.Transferred sidewall spacer etch process from development facility to largest manufacturing facility without significant issues; one of the few development to manufacturing transfers completed on time.Explored in-situ gate metrology systems, which had potential to eliminate several process steps and provide measurement data feedback in two minutes instead of twelve hours.Oxidation:Created new, single-wafer STI Liner oxide that simplified processing and reduced manufacturing costs.Developed ultra-thin gate base oxides and improved oxide anneals, extending the lifetime of the established gate technology and delaying the need for an expensive replacement technology by more than two years.Optimized poly-Si oxidation process to increase quality of oxides, reducing failures at final testing and increasing yield of sellable pieces by 30%.

Thin Films Module - Fab25 - Rapid Thermal Processing (RTP):Stabilized temperature measurement and improved tool control by replacing initial system pyrometers.Installed and verified production worthiness of HotLinersTM, which acted as a constant temperature body to eliminate variation due to differences in incoming material.Optimized temperature uniformity, enhancing process uniformity and product yield.Developed and optimized TiSi, CoSi and NiSi processes.Redefined calibration methods for tightened temperature control of AMAT RTP Chambers.Identified process sensitivities, which impacted electrical performance and took action to reduce their influence.Implemented Advanced Process Control and Fault Detection & Classification system, allowing the first real-time supervision of an RTP process.Supported worldwide AMD fabs with AMAT RTP issues by sharing personal best practices.Developed process monitors for temperature ranges and process environments that had not been possible to monitor before.Established preventative maintenance improvements to reduce tool downtime and increase utilization.

Lead engineer for "Stand-alone 0.25 µm RTP tool" project by managing SEMATECH's effort, which developed and improved Applied Materials' Centura RTP system. This next generation tool revolutionized the area of Rapid Thermal Processing and quickly dominated the market.

Designed digital module for the PATRIOT missile system's ground radar.Designed, simulated, modeled, and tested digital signal processing chips which included gate array, register, and custom circuitry.Team Leader for computer modeling of the digital signal processing chips to ease their incorporation into multiple other systems.