Deepika Pathak Email & Phone Number

Experienced VLSI & Embedded Systems professional with an MTech, currently ensuring quality and performance in Synopsys's Fusion Compiler Tool. Specializing in Static Timing Analysis (STA) product validation, I address customer RTL to GDSII timing issues and enhance tool quality by analyzing and resolving issues. Skilled in monitoring version changes and ensuring robust QoR, I bring strong analytical, communication, and detail-oriented capabilities. Passionate about physical design and committed to operational excellence, I thrive in collaborative environments. Let's connect to explore technical synergies and drive innovation together.

Listed skills include Cadence Virtuoso, Linux, Xilinx Vivado, Cadence Tempus, and 16 others.