John Scott Email & Phone Number

Austin, Texas Area

Austin, Texas Area

Project focus during this time was on A72 core for advanced multi-core digital networking processors. See below for further details.

Austin, Texas Area

ARM Core Physical Design - A7, A53, A57, A72 multi-gigahertz cores. Responsibilites included clock insertion (CTS and concurrent clock/data optimization), static timing analysis and timing takedown (base and noise) in multimode environment, synthesis, place and route, signoff timing optimization, and ECO implementation. Working in advanced nodes of 28nm and 16nm.Power-PC Core Physical Design - e200/e300/e500 and e5500/e6500 cores. Primary responsibilities included clock insertion… Show more ARM Core Physical Design - A7, A53, A57, A72 multi-gigahertz cores. Responsibilites included clock insertion (CTS and concurrent clock/data optimization), static timing analysis and timing takedown (base and noise) in multimode environment, synthesis, place and route, signoff timing optimization, and ECO implementation. Working in advanced nodes of 28nm and 16nm.Power-PC Core Physical Design - e200/e300/e500 and e5500/e6500 cores. Primary responsibilities included clock insertion (H-Tree and CTS) and custom clock scripting using internal tools. Additional responsibilites included a range of activities across synthesis, place and route, and static timing analysis. Show less

Austin, Texas Area

* 4 years experience as a library implementation engineer at the Somerset Design Center. Standard cell, data path, and semi-custom library cell flow supporting multiple design teams. Led timing characterization effort of cells and delivery of associated timing views.* 4 years experience as a device engineer in the Advanced Products Research and Development Laboratories (APRDL). Transistor module development for 0.25-0.38um CMOS/BiCMOS/SOI SRAM technologies. Process cornering for… Show more * 4 years experience as a library implementation engineer at the Somerset Design Center. Standard cell, data path, and semi-custom library cell flow supporting multiple design teams. Led timing characterization effort of cells and delivery of associated timing views.* 4 years experience as a device engineer in the Advanced Products Research and Development Laboratories (APRDL). Transistor module development for 0.25-0.38um CMOS/BiCMOS/SOI SRAM technologies. Process cornering for speed/yield analysis, bitcell characterization, and design liaison activities. Show less

Doctor Of Philosophy (Ph.D.), Electrical And Electronics Engineering

Thesis - MOS Device Design for Reduced Temperature Operation Advisor: Dr. James Plummer

Master Of Science (M.S.), Electrical Engineering

Bachelor Of Science (B.S.), Electrical Engineering